1. Field of the Invention
The present invention generally relates to a substrate and a method for manufacturing the same, and particularly relates to a substrate having a penetrating via penetrating the base member and wiring connected to the penetrating via, and a method for manufacturing the same.
2. Description of the Related Art
In these years, by using fine processing technology of manufacturing a semiconductor, packages called MEMS (Micro Electro Mechanical Systems) for a micro machine and a substrate such as an interposer mounting a semiconductor device therein, are developed. The above described substrate adopts a configuration wherein a penetrating via is formed in a through-hole penetrating a base member so as to electrically connect wirings formed on corresponding sides of the base member.
FIG. 1 is a cross-sectional view showing a substrate. As shown in FIG. 1, the substrate 10 comprises a silicon member 11, an insulating layer 13, penetrating vias 15, wirings 17 and 21, and solder resists 19 and 24. In the silicon member 11, through-holes 12 penetrating the silicon member 11 are formed. The insulating layer 13 is formed so as to cover the surface of the silicon member 11 where the through-holes 12 are formed. The insulating layer 13 is provided for insulating the penetrating via 15 and the wirings 17 and 21 from the silicon member.
The penetrating via 15 is provided in the through-hole 12 where the insulating layer 13 is formed. The penetrating via 15 has a cylindrical shape and an end part 15a of the penetrating via 15 and a surface 13a of the insulating layer 13 are to be coplanar and another end part 15b of the penetrating via 15 and another surface 13b of the insulating layer 13 are also to be coplanar. The penetrating via 15 is connected to the wirings 17 and 21 provided on corresponding sides of the silicon member 11. The penetrating via 15 is provided for electrically connecting the wirings 17 and 21 formed on corresponding sides of the silicon member 11.
The penetrating via 15 is provided by the following steps of: forming a seed layer by a spattering method on an upper surface of the silicon member 11 where the insulating layer 13 is formed and depositing a conductive metal layer on the seed layer by the elecrolytic plating method (See Patent Document 1, for example).
The wiring 17 which is connected to the edge part 15a of the penetrating via 15 comprises an external connection terminal 18. The external connection terminal 18 is connected to another substrate such as a motherboard 26. A solder resist layer 19 exposing the external connection terminal 18 is formed on the upper surface of the base member 11 so as to cover the wiring 17 except the external connection terminal 18.
The wiring 21 connected to the edge part 15b of the penetrating via 15 includes an external connection terminal 22. MEMS or a semiconductor device 25 are mounted on the external connection terminal 22. The solder resist 24 exposing the external connection terminal 22 is provided on an undersurface of the silicon member 11 so as to cover the wiring 21 except the external connection terminal 22.
However, the shape of the conventional penetrating via 15 is cylindrical, so that water infiltrates into a gap between the insulating layer 13 facing the penetrating via 15 and the penetrating via 15, and thereby, the penetrating via 15 is degraded and electrical connection reliability between the wirings 17, 21 and the penetrating via 15 is reduced.
Moreover, according to a conventional method for forming the penetrating via 15, a separat conductive metal layer on a surface of a seed layer is formed on inside edges of the through-hole 12 and the conductive metal layer is grown along the inside edges of the through-hole 12, and thus, a void (cavity) remains near the center of the penetrating via 15. Therefore, the electrical connection reliability of the penetrating via 15 connected to the wirings 17 and 21 is degraded.